5 分钟内开始你的第一个模拟电路设计。

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怎么开始第一次对话

AI 助手在右侧面板。第一次使用前，请先把 LLM Provider 的 API Key 配好（见 § 配置 LLM Provider）。

1. 把光标放进右下角输入框，直接用自然语言说出需求。
2. 按 Enter 发送；用 Shift+Enter 换行。
3. 对话头部的两个下拉框可以随时切换 Provider 和具体模型，更改会立即重连后端。
4. 顶部 EN | 中 开关同时控制界面语言和 LLM 回复语言 — 选了哪个，AI 就用哪个回。
5. 不知道说什么？聊天面板有 4 个快捷按钮，包括 “怎么使用？“，点一下让 AI 介绍系统能做什么。

左侧活动栏一览

窄窄的图标列从上到下依次是：

按钮	作用
目录 (Explorer)	项目文件树。展开 PROJECTS 看到所有 Library；右键空白区可以新建 Library。详见 § Explorer 数据结构。
知识库 (Packs)	已安装的 Pack 列表。Pack 是结构化的设计知识 — 每个 Pack 包含拓扑、规则、示例 netlist，AI 在生成电路时会优先复用。
技能 (Skills)	可加载的“方法库”。每个 Skill 是一段流程性的领域指引（如 gm/ID sizing、netlist review、TDD 调试）。AI 在执行任务时按需加载。
洞察 (Insights)	项目级 lessons：每次调试 / 优化沉淀下来的可复用经验，下次类似场景 AI 自动注入。
归档 (Archives)	历史会话与已完成的项目记录，便于回顾。
扩展 (Extensions)	查看当前注册的 hooks 与自定义工具（custom tools），可以热加载。
设置 (Settings)	配 LLM Provider、API Key、ngspice 路径、Brave Search Key、Sandbox 模式等。
AI	显示 / 隐藏右侧 AI 对话面板。

Explorer (目录) 的数据结构

采用 Cadence Virtuoso 风格的 Library → Cell → View 三层模型。安装后默认用户工作目录是 D:\CironaData\（可在 Settings → Data Directory 改）：

D:\CironaData\                  ← 用户工作目录（APP_DATA_ROOT，可在 Settings 修改）
├── .cirona\                    ← 全局配置（API Key、缓存、日志、user 层 acp.yaml）
│   ├── settings\               ← .env (API Key 等) + config.yaml
│   ├── cache\ logs\ data\      ← 运行时数据，可丢弃
│   └── lessons\ discussions\   ← 跨项目沉淀的洞察
├── pdk\                        ← 用户额外安装的 PDK（Settings → PDK Library 添加）
├── packs\                      ← 用户额外安装的 Pack
├── skills\                     ← 用户额外安装的 Skill
└── projects\                   ← 你所有项目（Library）的根目录
    ├── demo\                   ← 装机自带的 4-cell demo library
    │   ├── acp-project.yaml    ← 项目元数据 (含 pdk: 字段)
    │   ├── pdk\                ← junction → INSTALL_ROOT/backend/pdk (装机脚本建立)
    │   └── <cell>/             ← bandgap / fc_ota / two_stage / ldo
    └── <Library_A>\            ← 你自己创建的 Library
        ├── acp-project.yaml
        ├── pdk\<选的 PDK>\     ← junction → 真实 PDK 物理位置（创建时自动建）
        ├── .cirona\            ← 项目内部状态（sessions / history）
        ├── <Cell_1>\           ← 一个电路单元（如 my_ota）
        │   ├── design\         ← 网表 (.cir)
        │   ├── testbench\      ← Testbench (.sp)
        │   ├── simulation\     ← 仿真输出
        │   └── docs\           ← cell 级笔记
        └── <Cell_2>\ ...

三个根目录的关系：

• INSTALL_ROOT（程序安装目录，默认 C:\Program Files\Cirona\）— 只读，含 bundled PDK / Pack / Skill
• APP_DATA_ROOT（用户工作目录，默认 D:\CironaData\）— 读写，所有用户数据 / 配置 / 项目都在这里
• install.json（位于 %APPDATA%\Cirona\）— 记录用户在 Settings 选择的 Data Directory，跨版本保留

• Library：一个项目，对应一个目录。AI 会在 Library 级理解你的整体设计上下文。
• Cell：一个电路单元（OTA、bandgap、bias 等）。必须激活某个 Cell 才能让 AI 写文件 — 状态栏显示当前激活 Cell。
• View：Cell 内部的具体视图 — schematic、testbench、sim、docs 等子目录。

常用操作

• 右键 PROJECTS → New Library 新建项目。
• 右键 Library → New Cell 新建 Cell；选好 Cell 类型（OTA、Bandgap 等）。
• 双击 Cell 名 → 设为 Active Cell（状态栏 ⚡ 会显示）。
• 右键 Cell → Open in Workspace 用文件资源管理器打开。
• 双击文件 → 在中央编辑器里打开。

配置 LLM Provider

没配 API Key，AI 对话发不出去。两个入口都能配：

入口 A：AI 头部 ⚙️ — LLM 快速设置（推荐）

1. 点右上 AI 面板头部的齿轮图标，弹出 LLM 快速设置。
2. 选 Provider（默认 Anthropic Claude）；API URL 留空使用官方端点，如需第三方代理在这里改。
3. 填 API Key（输入框右侧 👁 可显示明文）。
4. 点 Test Connection 验证；成功后 API Key 行下方变绿色 ✓。
5. 点 保存。配置自动持久化，下次启动直接复用。

入口 B：左侧 ⚙️ Settings 面板（更全）

Settings 面板把所有 Provider 列出来，能管理多家的 Key、自定义 base URL、增删自定义模型 ID。还能配 ngspice 路径、Brave Search Key、Sandbox 模式等系统级选项。

支持的 Provider

Provider	典型模型	默认 URL
Anthropic Claude	claude-sonnet-4-6, claude-haiku-4-5	api.anthropic.com
Google Gemini	gemini-3-flash-preview, gemini-2.5-pro	SDK 直连
OpenAI	gpt-5.1, gpt-5.2, gpt-5.4 (默认), gpt-5.5	api.openai.com/v1
DeepSeek	deepseek-v4-flash, deepseek-v4-pro	api.deepseek.com
Zhipu GLM	glm-5, glm-5.1	open.bigmodel.cn
MiniMax	MiniMax-M2.7, MiniMax-M2.5	api.minimax.io/v1
Moonshot Kimi	k2.5	api.moonshot.cn/v1
Custom	任意 OpenAI 兼容端点	自填

Start your first analog circuit design in under 5 minutes.

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Starting Your First Conversation

The AI assistant is in the right panel. Before first use, configure your LLM Provider API Key (see § Configure LLM Provider).

1. Click into the input box at the bottom-right and type your requirements in natural language.
2. Press Enter to send; use Shift+Enter for a new line.
3. The two dropdowns at the top of the chat panel let you switch Provider and model at any time — changes reconnect immediately.
4. The EN | 中 toggle at the top controls both UI language and LLM response language — whatever you pick, the AI responds in that language.
5. Not sure what to ask? The chat panel has 4 quick-action buttons including “How do I use this?” — click it to get an introduction to what the system can do.

Activity Bar Overview

The narrow icon column from top to bottom:

Button	Function
Explorer (目录)	Project file tree. Expand PROJECTS to see all Libraries; right-click blank area to create a new Library. See § Explorer Data Structure.
Packs (知识库)	List of installed Packs. A Pack is structured design knowledge — each Pack contains topologies, rules, and example netlists that the AI reuses when generating circuits.
Skills (技能)	Loadable method library. Each Skill is a procedural domain guide (e.g., gm/ID sizing, netlist review, TDD debugging) loaded by the AI on demand.
Insights (洞察)	Project-level lessons: reusable insights accumulated from debugging and optimization, auto-injected by the AI in similar future scenarios.
Archives (归档)	Historical sessions and completed project records for reference.
Extensions (扩展)	View registered hooks and custom tools; hot-reloadable.
Settings (设置)	Configure LLM Provider, API Key, ngspice path, Brave Search Key, Sandbox mode, and other system settings.
AI	Show/hide the right-side AI conversation panel.

Explorer Data Structure

Uses a Cadence Virtuoso-style Library → Cell → View three-tier model. After install, the default user data directory is D:\CironaData\ (changeable in Settings → Data Directory):

D:\CironaData\                  ← User data root (APP_DATA_ROOT, configurable in Settings)
├── .cirona\                    ← Global config (API keys, cache, logs, user-layer acp.yaml)
│   ├── settings\               ← .env (API keys etc.) + config.yaml
│   ├── cache\ logs\ data\      ← Runtime data, safe to delete
│   └── lessons\ discussions\   ← Cross-project insights
├── pdk\                        ← Extra user-installed PDKs (Settings → PDK Library)
├── packs\                      ← Extra user-installed Packs
├── skills\                     ← Extra user-installed Skills
└── projects\                   ← All your projects (Libraries) live here
    ├── demo\                   ← Bundled 4-cell demo library
    │   ├── acp-project.yaml    ← Project metadata (incl. pdk: field)
    │   ├── pdk\                ← junction → INSTALL_ROOT/backend/pdk (built by installer)
    │   └── <cell>/             ← bandgap / fc_ota / two_stage / ldo
    └── <Library_A>\            ← Library you create
        ├── acp-project.yaml
        ├── pdk\<selected PDK>\ ← junction → real PDK location (auto-created at New Project)
        ├── .cirona\            ← Project state (sessions / history)
        ├── <Cell_1>\           ← Circuit cell (e.g., my_ota)
        │   ├── design\         ← Netlists (.cir)
        │   ├── testbench\      ← Testbenches (.sp)
        │   ├── simulation\     ← Simulation output
        │   └── docs\           ← Cell-level notes
        └── <Cell_2>\ ...

Three root directories:

• INSTALL_ROOT (program install dir, default C:\Program Files\Cirona\) — read-only, contains bundled PDK / Pack / Skill
• APP_DATA_ROOT (user data dir, default D:\CironaData\) — read-write, all user data / config / projects
• install.json (in %APPDATA%\Cirona\) — records the Data Directory you selected in Settings; persists across versions

• Library: One project, one directory. The AI understands your overall design context at the Library level.
• Cell: One circuit unit (OTA, bandgap, bias, etc.). A Cell must be activated before the AI can write files — the status bar shows the currently active Cell.
• View: Specific views inside a Cell — schematic, testbench, sim, docs subdirectories.

Common Operations

• Right-click PROJECTS → New Library to create a project.
• Right-click Library → New Cell to create a Cell; select the Cell type (OTA, Bandgap, etc.).
• Double-click a Cell name → set as Active Cell (⚡ appears in status bar).
• Right-click Cell → Open in Workspace to open in File Explorer.
• Double-click a file → opens in the central editor.

Configure LLM Provider

Without an API Key, AI conversations cannot be sent. There are two entry points:

Entry A: AI Panel ⚙️ — LLM Quick Settings (Recommended)

1. Click the gear icon in the AI panel header (top-right) to open LLM Quick Settings.
2. Select a Provider (default: Anthropic Claude). Leave API URL blank to use the official endpoint; fill it in for a third-party proxy.
3. Enter your API Key (click 👁 on the right to show plaintext).
4. Click Test Connection to verify; on success, a green ✓ appears below the API Key field.
5. Click Save. The configuration is persisted automatically and reused on next launch.

Entry B: Left ⚙️ Settings Panel (Full Options)

The Settings panel lists all Providers and lets you manage API keys, custom base URLs, and custom model IDs for multiple providers. Also configures ngspice path, Brave Search Key, Sandbox mode, and other system-level options.

Supported Providers

Provider	Typical Models	Default URL
Anthropic Claude	claude-sonnet-4-6, claude-haiku-4-5	api.anthropic.com
Google Gemini	gemini-3-flash-preview, gemini-2.5-pro	SDK direct
OpenAI	gpt-5.1, gpt-5.2, gpt-5.4 (default), gpt-5.5	api.openai.com/v1
DeepSeek	deepseek-v4-flash, deepseek-v4-pro	api.deepseek.com
Zhipu GLM	glm-5, glm-5.1	open.bigmodel.cn
MiniMax	MiniMax-M2.7, MiniMax-M2.5	api.minimax.io/v1
Moonshot Kimi	k2.5	api.moonshot.cn/v1
Custom	Any OpenAI-compatible endpoint	User-defined

v3 采用 Virtuoso 风格的 Library → Cell → View 层级结构管理项目。

核心概念

• Library（库）— 一个项目文件夹，包含多个 Circuit Cell，元数据存储在 acp-project.yaml
• Cell（单元）— 单个电路模块（如 “ota”、“comparator”），每个 Cell 包含完整的设计文件
• View（视图）— 同一 Cell 的不同表示：网表、testbench、仿真结果、报告

项目结构

my_project/                       # Library（项目根目录）
├── acp-project.yaml              # 项目配置（PDK、Cell 列表、状态）
├── pdk/<pdk_name>/             # PDK junction（指向 backend/pdk/）
├── my_ota/                       # Cell: OTA 电路
│   ├── design/                   # 网表文件 (.cir, .sp)
│   │   └── my_ota.cir
│   ├── testbench/                # 测试激励
│   │   ├── tb_op.sp              # DC 工作点
│   │   └── tb_ac.sp              # AC 频率响应
│   ├── simulation/               # 仿真输出（波形数据）
│   └── reports/                  # 分析报告
├── my_comparator/                # Cell: 比较器
│   ├── design/
│   ├── testbench/
│   └── ...
└── .cirona/              # 项目级配置（不入 git）
    ├── settings/config.yaml      # 项目级设置覆盖
    ├── history/sessions/         # 会话历史
    └── knowledge.md              # 项目设计知识（AI 自动维护）

新建项目

1. 点击菜单 File → New Project 或主界面 New Project
2. 输入项目名称
3. 选择目标 PDK（vpdk180nm / vpdk55nm / sky130，或自己装的 PDK）
4. 点击 Create，系统自动生成 acp-project.yaml 和目录结构

Cell 状态追踪

状态	说明
pending	已创建，尚未开始设计
in_progress	设计进行中
verified	仿真验证通过
failed	仿真未达标，需要调试

v3 uses a Virtuoso-style Library → Cell → View hierarchy to manage projects.

Core Concepts

• Library — A project folder containing multiple Circuit Cells; metadata stored in acp-project.yaml
• Cell — A single circuit module (e.g., “ota”, “comparator”) with all its design files
• View — Different representations of the same Cell: netlist, testbench, simulation results, reports

Project Structure

my_project/                       # Library (project root)
├── acp-project.yaml              # Project config (PDK, Cell list, status)
├── pdk/<pdk_name>/             # PDK junction (points to backend/pdk/)
├── my_ota/                       # Cell: OTA circuit
│   ├── design/                   # Netlist files (.cir, .sp)
│   │   └── my_ota.cir
│   ├── testbench/                # Test stimulus
│   │   ├── tb_op.sp              # DC operating point
│   │   └── tb_ac.sp              # AC frequency response
│   ├── simulation/               # Simulation output (waveform data)
│   └── reports/                  # Analysis reports
├── my_comparator/                # Cell: Comparator
│   ├── design/
│   ├── testbench/
│   └── ...
└── .cirona/                   # Project-level config (not in git)
    ├── settings/config.yaml      # Project-level settings overrides
    ├── history/sessions/         # Session history
    └── knowledge.md              # Project design knowledge (AI-maintained)

Create a New Project

1. Click menu File → New Project or the main screen's New Project button
2. Enter the project name
3. Select the target PDK (vpdk180nm / vpdk55nm / sky130, or one you installed)
4. Click Create — acp-project.yaml and the directory structure are created automatically

Cell Status Tracking

Status	Description
pending	Created, design not yet started
in_progress	Design in progress
verified	Simulation verification passed
failed	Simulation did not meet specs; debugging needed

VS Code 风格的文件浏览器，位于左侧栏 Explorer 面板。

基本操作

• 单击文件夹 — 展开/折叠目录
• 单击文件 — 在编辑器中打开
• 右键菜单 — 新建文件、新建文件夹、重命名、删除

工具栏按钮

• New File — 在当前选中文件夹下新建文件
• New Folder — 新建子目录
• Refresh — 重新加载文件树
• Close — 关闭当前项目

文件图标

图标	类型
SPICE 图标	SPICE 文件（.sp, .cir, .spice）
库文件图标	Library 文件（.lib）
Python 图标	Python 脚本（.py）
配置图标	JSON / YAML 配置文件
Cell 图标	Cell 目录（含 design/ 子目录）

A VS Code-style file browser located in the left sidebar Explorer panel.

Basic Operations

• Click a folder — Expand/collapse directory
• Click a file — Open in the editor
• Right-click menu — New file, new folder, rename, delete

Toolbar Buttons

• New File — Create a file in the currently selected folder
• New Folder — Create a subdirectory
• Refresh — Reload the file tree
• Close — Close the current project

File Icons

Icon	Type
SPICE icon	SPICE files (.sp, .cir, .spice)
Library icon	Library files (.lib)
Python icon	Python scripts (.py)
Config icon	JSON / YAML configuration files
Cell icon	Cell directories (containing design/ subdirectory)

基于 Monaco Editor（VS Code 同款引擎），支持 SPICE 语法高亮。

功能特性

• SPICE 语法高亮 — 关键字、注释、数值自动着色
• 行号显示 — 方便定位和调试
• 多 Tab 支持 — 同时打开多个文件
• 未保存提示 — Tab 上显示圆点标记
• Minimap — 长文件概览

编辑器快捷键

快捷键	功能
Ctrl+S	保存当前文件
Ctrl+Z	撤销
Ctrl+Shift+Z	重做
Ctrl+F	查找
Ctrl+H	查找替换
Ctrl+/	切换注释
Ctrl+D	复制当前行

Markdown 预览

打开 .md 文件时，编辑器自动切换为 Markdown 渲染预览模式，支持表格、代码块、公式等格式。

预览顶部有 Edit 按钮，点击可切换回 Monaco 源码编辑模式。切换到其他文件 Tab 后再切回也会恢复预览。

图片预览

打开 PNG / JPG / SVG 等图片文件时，编辑区会直接显示图片预览。

Built on Monaco Editor (the same engine as VS Code), with SPICE syntax highlighting.

Features

• SPICE syntax highlighting — Keywords, comments, and values auto-colored
• Line numbers — Easy navigation and debugging
• Multi-tab support — Open multiple files simultaneously
• Unsaved indicator — Dot marker on the Tab
• Minimap — Overview for long files

Editor Shortcuts

Shortcut	Function
Ctrl+S	Save current file
Ctrl+Z	Undo
Ctrl+Shift+Z	Redo
Ctrl+F	Find
Ctrl+H	Find & Replace
Ctrl+/	Toggle comment
Ctrl+D	Duplicate current line

Markdown Preview

Opening a .md file automatically switches to Markdown rendered preview mode, supporting tables, code blocks, formulas, and more.

The Edit button at the top of the preview switches back to Monaco source editing mode. Switching to another Tab and back also restores preview.

Image Preview

Opening PNG / JPG / SVG and other image files displays an inline image preview in the editor area.

Pack 是 Cirona 的核心创新 — 可版本化的自包含知识模块。每个 Pack 把“一个电路族 / 一个 PDK / 一组通用基础”的知识、参考实现、自定义工具和方法论打包在一起，可以独立安装、卸载、版本升级，互不影响。

Pack 类型

电路族 Pack（Circuit Pack）

针对特定电路拓扑的领域知识 + 参考网表 + sizing 套路 + 调试 playbook：

Pack	内容
pack-5t-ota	5 管 OTA（教学起点、最小可工作 OTA）
pack-folded-cascode-ota	折叠共源共栅 OTA（宽摆镜像、Gmid sizing 流程、cascode 偏置生成）
pack-telescopic-ota	套筒式 OTA（高增益、低 swing 场景）
pack-two-stage-ota	两级 OTA（Miller 补偿、PSRR 优化）
pack-bandgap	带隙基准（PNP-based 核心 / startup 电路 / PSRR 优化 / temp coefficient）
pack-ldo	LDO 稳压器（dropout / load & line regulation / loop stability / iload corner stress）
pack-comparator	比较器（latch / preamp / metastability / kickback noise）

PDK Pack（PDK 知识）

每个 bundled PDK 配套的 metadata + 器件模型说明 + corner 文件位置：

Pack	内容
pack-pdk-vpdk180nm	vpdk180nm 工艺规则、器件参数、corner 模型
pack-pdk-vpdk55nm	vpdk55nm 工艺规则、器件参数
pack-pdk-sky130	SkyWater sky130 工艺规则、可流片提示

PDK Pack 由 auto_activate_pdk 机制自动激活：当你新建 Library 选了某个 PDK，对应的 PDK Pack 会一并加载。

基础设施 Pack（始终激活）

Pack	内容
analog-basics	14 个基础器件模块（active-load / bias-generator / cascode / cmfb / common-gate-stage / common-source / comparator-latch / current-mirror / differential-pair / miller-compensation / output-stage / resistive-load / source-follower / switch）+ V4 认知架构铁律 + sizing 五步法 + 共享元数据
pack-ngspice	ngspice 语法 / 控制语言 / 常见陷阱（多次 op 跨 plot scope、AC tb 模板坑、param 语法等）

Pack 自动激活

三种激活方式：

• 关键词触发 — 你的请求里含有 “folded-cascode OTA” / “bandgap” / “LDO” 等关键词，对应电路族 Pack 自动加载
• PDK 绑定 — 新建 Library 选了某 PDK，该 PDK 的 Pack 自动激活
• 始终在线 — 基础设施 Pack（analog-basics + pack-ngspice）始终激活

Pack 目录

所有 Pack 在 backend/packs/ 下，每个 Pack 是一个文件夹结构：

backend/packs/<pack_name>/
├── manifest.yaml                     # 元数据（name / version / depends / activate-keywords）
├── knowledge/blocks/<cell>/          # 该 Pack 的知识章节（*.md）
├── skills/<skill>/SKILL.md           # Pack 私有的方法论（可选）
├── tools/<tool>/                     # Pack 自定义工具（可选）
└── assets/                           # 参考网表、testbench、图片

把自己的 Pack 放进去后，运行 /skills reload 重新扫描即可生效。

Pack Builder（从设计导出 Pack）

完成一次电路设计后，可以将设计过程中积累的知识提炼为可复用的 Pack：

/export-pack <pack_name>    # 将当前设计导出为 Pack 草稿

导出流程由 pack_builder Skill 驱动，自动提炼：

• design_flow.md — 从对话历史提取的分阶段设计流程
• failure_playbook.md — 从调试经验提取的故障诊断手册
• overview.md — 电路架构概述、端口定义、仿真结果汇总
• reference_designs/ — 参考网表和 testbench

草稿先写入 .cirona/pack-drafts/，审阅满意后用 publish 命令发布到 backend/packs/。

Packs are a core innovation of Cirona — versioned, self-contained knowledge modules. Each Pack bundles “one circuit family / one PDK / one set of universal foundations” with knowledge, reference implementations, custom tools, and methodology — install / uninstall / version-bump independently without affecting other Packs.

Pack Types

Circuit Pack

Domain knowledge + reference netlists + sizing recipes + debugging playbook for specific circuit topologies:

Pack	Content
pack-5t-ota	5-transistor OTA (teaching starter, minimum-viable OTA)
pack-folded-cascode-ota	Folded-cascode OTA (wide-swing mirrors, Gmid sizing flow, cascode bias generation)
pack-telescopic-ota	Telescopic OTA (high-gain, narrow-swing scenarios)
pack-two-stage-ota	Two-stage OTA (Miller compensation, PSRR optimization)
pack-bandgap	Bandgap reference (PNP-based core, startup circuit, PSRR optimization, temp coefficient)
pack-ldo	LDO regulator (dropout, load & line regulation, loop stability, iload corner stress)
pack-comparator	Comparator (latch / preamp / metastability / kickback noise)

PDK Pack

Metadata + device-model usage guide + corner-file location for each bundled PDK:

Pack	Content
pack-pdk-vpdk180nm	vpdk180nm process rules, device parameters, corner models
pack-pdk-vpdk55nm	vpdk55nm process rules, device parameters
pack-pdk-sky130	SkyWater sky130 process rules, tape-out tips

PDK Packs are loaded by the auto_activate_pdk mechanism: pick a PDK when creating a Library, and the matching PDK Pack comes online automatically.

Infrastructure Packs (always-on)

Pack	Content
analog-basics	14 fundamental device modules (active-load / bias-generator / cascode / cmfb / common-gate-stage / common-source / comparator-latch / current-mirror / differential-pair / miller-compensation / output-stage / resistive-load / source-follower / switch) + V4 cognitive-architecture iron laws + sizing five-step recipe + shared metadata
pack-ngspice	ngspice syntax / control language / common pitfalls (cross-op plot scope, AC testbench template gotchas, .param syntax, etc.)

Auto-Activation

Three activation paths:

• Keyword trigger — your prompt contains “folded-cascode OTA” / “bandgap” / “LDO” etc., the matching circuit Pack loads
• PDK binding — pick a PDK in a Library, that PDK's Pack activates
• Always-on — infrastructure Packs (analog-basics + pack-ngspice) are always loaded

Pack Directory

All Packs live under backend/packs/. Each Pack is a directory:

backend/packs/<pack_name>/
├── manifest.yaml                     # Metadata (name / version / depends / activate-keywords)
├── knowledge/blocks/<cell>/          # Knowledge chapters (*.md)
├── skills/<skill>/SKILL.md           # Pack-private methodology (optional)
├── tools/<tool>/                     # Pack custom tools (optional)
└── assets/                           # Reference netlists, testbenches, images

Drop your own Pack here and run /skills reload to rescan.

Pack Builder (Export Design as Pack)

After completing a circuit design, distill accumulated knowledge into a reusable Pack:

/export-pack <pack_name>    # Export current design as a Pack draft

The export is driven by the pack_builder Skill and automatically extracts:

• design_flow.md — Phased design flow extracted from conversation history
• failure_playbook.md — Fault diagnosis playbook extracted from debugging experience
• overview.md — Circuit architecture overview, port definitions, simulation results summary
• reference_designs/ — Reference netlists and testbenches

Drafts are first written to .cirona/pack-drafts/; after review, use the publish command to release to backend/packs/.

Skill 是方法论插件，教 AI 怎样做设计，与 Pack 提供的领域知识互补。

内置 Skill

Skill	功能
analog_design_flow	模拟电路设计方法论（5 阶段流程）
gmid_sizing	Gmid sizing 晶体管尺寸方法（直接读 PDK 预生成的 gm/Id lookup table）
sdas	Spec-Driven Architecture Screening（需求驱动的架构筛选）
tdd	Test-Driven Debugging（DC First 测试驱动调试）
netlist_review	网表审查（仿真前自动检查）

Skill 管理命令

/skills reload        # 重新扫描 skill 目录
/skill list           # 列出已安装的 skill
/skill install <url>  # 从 URL 安装 skill
/skill remove <name>  # 卸载 skill

Skill vs Pack

	Pack	Skill
定位	领域知识（“什么电路、怎么连”）	方法论（“怎么做设计”）
激活方式	关键词自动激活	/skill 命令手动加载
存放位置	packs/	backend/skills/
可扩展	直接放文件夹	URL 安装 / 本地添加

Skills are methodology plugins that teach the AI how to design — complementing the domain knowledge provided by Packs.

Built-in Skills

Skill	Function
analog_design_flow	Analog circuit design methodology (5-stage flow)
gmid_sizing	Gmid sizing — pick W/L by reading the PDK's pre-computed gm/Id lookup table
sdas	Spec-Driven Architecture Screening
tdd	Test-Driven Debugging (DC First strategy)
netlist_review	Netlist review (automatic pre-simulation check)

Skill Management Commands

/skills reload        # Rescan the skills directory
/skill list           # List installed skills
/skill install <url>  # Install a skill from URL
/skill remove <name>  # Uninstall a skill

Skills vs Packs

	Pack	Skill
Role	Domain knowledge (“what circuit, how to connect”)	Methodology (“how to do the design”)
Activation	Keyword auto-activation	Manual load via /skill command
Location	packs/	backend/skills/
Extensible	Drop folder in packs/	Install from URL / add locally

右侧的 AI 对话面板是你的智能设计搭档，基于自研 Agent Engine 驱动。

使用方式

1. 在输入框中用自然语言描述需求
2. 按 Enter 发送（Shift+Enter 换行）
3. AI 会自动调用工具（读写文件、运行仿真、搜索知识库等）
4. 随时用 ESC 取消正在进行的操作

示例提问

电路设计

“设计一个两级 Miller 补偿 OTA，增益 > 60dB，GBW > 10MHz”
“用 180nm 工艺设计一个 bandgap reference，输出 1.2V”
“设计一个 StrongARM 比较器”

仿真与分析

“运行 AC 仿真，看看增益和相位裕度”
“分析一下为什么增益只有 40dB”
“帮我调一下 Miller 电容，相位裕度要 > 60 度”

知识查询

“搜索知识库，有哪些 OTA 拓扑可以选择？”
“折叠共源共栅和套筒式的区别是什么？”
“gm/ID 方法的设计流程是怎样的？”

The AI conversation panel on the right is your intelligent design partner, powered by a proprietary Agent Engine.

How to Use

1. Describe your requirements in natural language in the input box
2. Press Enter to send (Shift+Enter for new line)
3. The AI automatically invokes tools (read/write files, run simulation, search knowledge base, etc.)
4. Press ESC at any time to cancel an in-progress operation

Example Queries

Circuit Design

“Design a two-stage Miller-compensated OTA with gain > 60 dB and GBW > 10 MHz”
“Design a bandgap reference in 180nm process, output 1.2V”
“Design a StrongARM comparator”

Simulation & Analysis

“Run AC simulation, check gain and phase margin”
“Analyze why gain is only 40 dB”
“Help me tune the Miller capacitor to achieve phase margin > 60 degrees”

Knowledge Queries

“Search the knowledge base for available OTA topologies”
“What is the difference between folded-cascode and telescopic OTA?”
“What is the gm/ID design flow?”

Cirona 通过 Plan Mode（任务级开关）+ Sandbox 级别（系统级开关）两层组合控制 AI 自主度。

Plan 模式（任务级）

输入 /plan 切换 Plan 模式。在此模式下，AI 只做分析和规划，不执行任何文件修改操作 —— 适合先看设计方案再决定是否执行。再次输入 /plan 退出。

Sandbox 级别（系统级）

Settings 面板的 Sandbox 下拉切换三档安全级别：

级别	读权限	写权限	典型场景
strict	只能读 workdir 内文件	只能写 workdir	不信任的 AI 任务、纯 sandbox 验证
standard（默认）	能读全局（含 PDK / Knowledge）	只能写 workdir	大部分日常设计任务
permissive	全开	全开（仅拦毁灭性命令）	需要让 AI 改全局配置 / 安装新 Pack 等

AI 模型选择

对话头部下拉直接切 Provider + 具体模型，或用 /model 命令。完整支持的 Provider 列表见 § 配置 LLM Provider。常用模型：

Provider	典型模型	Thinking
Anthropic Claude	claude-sonnet-4-6, claude-haiku-4-5	✓
Google Gemini	gemini-3-flash-preview（默认），gemini-2.5-pro	✓
DeepSeek	deepseek-v4-flash, deepseek-v4-pro	✓
Zhipu GLM	glm-5, glm-5.1	—
Moonshot Kimi	k2.5	—
MiniMax	MiniMax-M2.7, MiniMax-M2.5	—
OpenAI	gpt-5.4（默认），gpt-5.1/5.2/5.5	—

Thinking 深度思考

在左下角 Settings 面板中可以开启/关闭 Thinking 模式。开启后 AI 会展示思考过程（紫色可折叠块），有助于理解设计决策的推理链。

Cirona controls AI autonomy through two layers: Plan Mode (per-task toggle) + Sandbox levels (system-wide).

Plan Mode (per-task)

Type /plan to enter Plan mode. In this mode, the AI only analyzes and plans — no file modifications. Useful for reviewing a design proposal before committing. Type /plan again to exit.

Sandbox Levels (system-wide)

The Sandbox dropdown in the Settings panel selects one of three safety tiers:

Level	Read	Write	When to use
strict	workdir only	workdir only	Untrusted AI tasks, pure sandbox validation
standard (default)	Global read (incl. PDK / Knowledge)	workdir only	Most everyday design tasks
permissive	Full	Full (only destructive commands blocked)	When AI needs to modify global config / install new Packs

AI Model Selection

Use the dropdowns at the top of the chat panel to switch Provider + specific model, or use the /model command. Full Provider list: see § Configure LLM Provider. Common models:

Provider	Typical models	Thinking
Anthropic Claude	claude-sonnet-4-6, claude-haiku-4-5	✓
Google Gemini	gemini-3-flash-preview (default), gemini-2.5-pro	✓
DeepSeek	deepseek-v4-flash, deepseek-v4-pro	✓
Zhipu GLM	glm-5, glm-5.1	—
Moonshot Kimi	k2.5	—
MiniMax	MiniMax-M2.7, MiniMax-M2.5	—
OpenAI	gpt-5.4 (default), gpt-5.1/5.2/5.5	—

Thinking / Deep Reasoning

Toggle Thinking mode in the Settings panel. When enabled, the AI displays its reasoning process as a collapsible purple block — helpful for understanding the rationale behind design decisions.

设计流程

AI Agent 遵循标准化的 5 阶段设计流程：

Design Flow

The AI Agent follows a standardized 5-stage design flow:

AI 辅助调试

仿真结果不达标时，AI 会自动：

• 分析 DC 工作点，检查每个晶体管是否在饱和区
• 查阅 failure playbook 中的已知问题模式
• 提出针对性的参数调整方案
• 重新仿真验证改进效果

自动化优化

左侧栏 Optimization 面板（也可以让 AI 调 optimize 工具）提供参数空间自动搜索，底层走 optuna：

算法	说明
bayesian	贝叶斯优化（TPE）— 高效收敛到单目标最优，适合 30–100 trials 内拿出可用解
cma_es	CMA-ES 协方差矩阵自适应进化策略 — 连续参数空间的全局优化，对地形复杂的问题更稳
multi_objective	NSGA-II 多目标 Pareto — 同时优化多个互相冲突的指标（例如增益 ↔ 功耗），返回 Pareto frontier 让你挑权衡点

所有算法支持 PVT corner sweep（pvt_scan 工具），把 typical / fast / slow / hot / cold 几个 corner 都跑一遍再综合打分。

常见优化场景

“相位裕度只有 45 度，帮我改到 60 度以上”
“功耗太高了，能不能在保持增益的前提下降低电流？”
“CMRR 不够，怎么改进差分对的匹配？”

AI-Assisted Debugging

When simulation results don't meet specs, the AI automatically:

• Analyzes DC operating points to check whether each transistor is in saturation
• Consults the failure playbook for known problem patterns
• Proposes targeted parameter adjustment plans
• Re-simulates to verify the improvement

Automated Optimization

The left-sidebar Optimization panel (or have the AI call the optimize tool) runs parameter-space search backed by optuna:

Algorithm	Description
bayesian	Bayesian optimization (TPE) — efficient convergence to a single-objective optimum, usually finds a usable solution within 30–100 trials
cma_es	CMA-ES (Covariance Matrix Adaptation Evolution Strategy) — global optimization in continuous spaces, more robust on rugged loss landscapes
multi_objective	NSGA-II multi-objective Pareto — optimizes several conflicting metrics simultaneously (e.g. gain ↔ power) and returns the Pareto frontier so you can pick the trade-off

All algorithms support PVT-corner sweeps via the pvt_scan tool — runs typical / fast / slow / hot / cold and aggregates the score.

Common Optimization Requests

“Phase margin is only 45°, help me get it above 60°”
“Power consumption is too high — can we reduce current while maintaining gain?”
“CMRR is insufficient — how do we improve differential pair matching?”

网表定义电路拓扑，以 .subckt 子电路封装。存放在 Cell 的 design/ 目录中。

基本结构

* 电路名称和描述
* 设计日期和作者

.subckt MY_OTA inp inn out vdd vss ibias
* --- 差分输入对 ---
MN1 net1 inp net_tail vss nmos W=10u L=500n m=4
MN2 net2 inn net_tail vss nmos W=10u L=500n m=4
* --- 尾电流源 ---
MN_TAIL net_tail ibias vss vss nmos W=5u L=1u m=8
* --- 有源负载 ---
MP1 net1 net1 vdd vdd pmos W=20u L=500n m=4
MP2 out net1 vdd vdd pmos W=20u L=500n m=4
.ends MY_OTA

网表规则

器件语法

器件	语法
MOSFET	Mname D G S B model W=... L=... m=...
电阻	Rname N+ N- value
电容	Cname N+ N- value
电压源	Vname N+ N- DC value
电流源	Iname N+ N- DC value

The netlist defines the circuit topology, encapsulated as a .subckt sub-circuit. Stored in the Cell's design/ directory.

Basic Structure

* Circuit name and description
* Design date and author

.subckt MY_OTA inp inn out vdd vss ibias
* --- Differential input pair ---
MN1 net1 inp net_tail vss nmos W=10u L=500n m=4
MN2 net2 inn net_tail vss nmos W=10u L=500n m=4
* --- Tail current source ---
MN_TAIL net_tail ibias vss vss nmos W=5u L=1u m=8
* --- Active load ---
MP1 net1 net1 vdd vdd pmos W=20u L=500n m=4
MP2 out net1 vdd vdd pmos W=20u L=500n m=4
.ends MY_OTA

Netlist Rules

Device Syntax

Device	Syntax
MOSFET	Mname D G S B model W=... L=... m=...
Resistor	Rname N+ N- value
Capacitor	Cname N+ N- value
Voltage source	Vname N+ N- DC value
Current source	Iname N+ N- DC value

* Testbench: AC 分析
* 用途: 测量增益、带宽、相位裕度

* === 引用 ===
.lib “../../pdk/vpdk180nm/models.lib” tt
.include “../design/my_ota.cir”

* === 选项 ===
.option post accurate

* === 电源 ===
VDD vdd 0 DC 1.8
VSS vss 0 DC 0

* === 偏置 ===
IBIAS ibias 0 DC 20u

* === 输入激励 ===
VIN_CM inp 0 DC 0.9
VIN_DM inp inn DC 0 AC 1
VCM inn 0 DC 0.9

* === 被测电路 ===
XDUT inp inn out vdd vss ibias MY_OTA

* === 负载 ===
CL out 0 10p

* === 分析 ===
.ac dec 100 1 1G

* === 测量 ===
.measure ac gain_db MAX vdb(out)
.measure ac ugf WHEN vdb(out)=0
.measure ac phase_at_ugf FIND vp(out) WHEN vdb(out)=0

.end

Testbench 检查清单

• .include PDK 模型库
• .include 被测电路网表
• 定义所有电源（VDD、VSS）
• 定义偏置条件（IBIAS 等）
• 添加输入激励
• 实例化 DUT（被测电路）
• 添加负载条件
• 指定分析类型
• 添加 .measure 提取指标
• 以 .end 结尾

Testbench Checklist

• .include PDK model library
• .include DUT netlist
• Define all power supplies (VDD, VSS)
• Define bias conditions (IBIAS, etc.)
• Add input stimulus
• Instantiate the DUT
• Add load conditions
• Specify analysis type
• Add .measure statements to extract metrics
• End with .end

什么是 vpdk？

vpdk = “virtual PDK” 的缩写。Cirona 自带的两个 vpdk（vpdk180nm / vpdk55nm）是为了让用户开箱即用就能跑完整设计流程而做的合成 PDK。它们提供了完整的 BSIM 模型 + gm/Id lookup 表 + corner 文件，让你不用先去找 foundry NDA 就能体验整套设计 / 仿真 / 优化流程。

它们不替代真实工艺，参数不对应任何 foundry，纯粹用于教学、算法验证、产品演示。要走真实流片，请用 sky130（Apache 2.0 真实开源工艺）或自己装 foundry PDK。

内置 PDK

Cirona 首版自带 3 个 PDK，安装后位于安装目录下的 backend/pdk/：

PDK	工艺	VDD	用途	可流片
vpdk180nm	通用 180nm BSIM3v3	1.8V core / 3.3V IO	入门、教学、算法验证	❌
vpdk55nm	低功耗 55nm BSIM4 v4.5	1.2V core / 1.8V IO	低噪声 / 高速电路 demo	❌
sky130	SkyWater 开源 130nm	1.8V	真实工艺	✅

添加自己的 PDK — Settings UI 一键搞定

需要用商业 foundry PDK（含 NDA）或自己编写的 PDK？通过 Settings 面板加进来。

Settings → PDK Library 区的样子：

┌─ PDK Library ───────────────────────────────────┐
│  ✓ vpdk180nm   bundled    🔒 (read-only)        │
│  ✓ vpdk55nm    bundled    🔒                    │
│  ✓ sky130      bundled    🔒                    │
│  ✓ tsmc28      D:\foundry\tsmc28\        🗑     │  ← 自己加的，可删
│                                                  │
│  [➕ 添加 PDK…]   [🔄 刷新]                     │
└──────────────────────────────────────────────────┘

添加 PDK 操作 5 步：

1. 左下角 ⚙️ Settings → 滚到 PDK Library 区
2. 点 ➕ 添加 PDK… 按钮
3. 系统对话框选择 PDK 目录（必须含 config/pdk_config.json）
4. 给 PDK 命名（字母开头，仅 a-zA-Z0-9_-，长度 2–40）
5. Cirona 把你选的绝对路径直接记录到用户层 acp.yaml 的 managed-block，不复制 / 不建 junction。即“reference 引用模式” — WYSIWYG，你选什么路径，yaml 写什么路径

添加完成后，PDK 立刻出现在 Settings 列表里（带源路径 tooltip），新建 Library 对话框的下拉里也能选到，无需重启。

可选模式（POST API 的 mode 字段）：junction 在 <APP_DATA_ROOT>/pdk/<name>/ 建一层 junction（适合想把所有 PDK 引用集中在一处方便 backup 的用户）；copy 把源 deep copy 进去（项目级自包含，但占空间）。两者都是 opt-in，UI 默认走 reference。

删除 PDK：在 Settings → PDK Library 选 PDK → 点垃圾桶图标 → 确认。删除时只 rmdir 链接本身，不会跟进 junction 删源文件。bundled 三个不可删（前端会提示）。

新建 Library 时选 PDK

每个新 Library 必须选一个 PDK：

1. 左侧 Explorer → + New Project → 选 Library 类型
2. 输入 Library 名 + 从下拉选 PDK（3 bundled + 你装的）
3. Cirona 自动在 <library>/pdk/<选的 PDK>/ 创建 junction → 真实 PDK 物理位置

Library 内部 testbench 都用相对路径 .lib “../../pdk/<pdk>/<lib>” tt，第一段穿过 junction 解析到真实 PDK。这种设计让 library 可以备份 / 跨机器拷贝（只要重建 junction）。

事后改 Library 的 PDK

Library 创建后想换 PDK：在 Explorer 里 右键 Library 名 → 选 Change PDK… → 弹窗下拉选新 PDK → Switch。Cirona 会替换 <library>/pdk/ junction 指向新 PDK 物理位置。注意：旧 testbench 里 .lib “../../pdk/<旧 PDK 名>/...” 字符串不会自动改名（PDK 名子目录变了），需要你手动更新或重新生成 testbench。

Demo Library 是特殊情况

projects/demo/ 是 mixed-PDK library（4 个 cell 用 vpdk180nm 和 vpdk55nm 两种 PDK），它的 pdk/ junction 直接指向 PDK 集合根（不是单 PDK）。装机时由安装程序自动建立 junction。

如果 demo 跑不起来报“找不到 .lib”，多半是 junction 失效（例如安装目录搬迁、跨机器拷贝、手动删过 pdk 目录）。修复办法：跑一次安装目录里的 scripts\install_demo_junction.bat（Windows）或 scripts/install_demo_junction.sh（Unix），脚本会自动重建 junction。

gm/ID 特性数据

每个 PDK 默认带 gm_id_data/ 子目录（gm/Id lookup 表），让 gmid_sizing skill 能直接给出尺寸建议而不必每次重新 sweep。如果你装的 PDK 没带这个，sizing 仍然能跑（动态 sweep），只是慢一点。

Iron Laws（铁律）

• 不要直接编辑 acp.yaml 或 install.json 来加 PDK — 用 Settings UI（UI 会做路径校验、命名校验、junction 安全删除等保护）
• 不要把 PDK 文件复制到 library 内 — library 只持有 junction
• testbench 内永远写相对路径 ../../pdk/<name>/<lib>，不写绝对路径

What is a “vpdk”?

vpdk is short for “virtual PDK”. Cirona ships two vpdks (vpdk180nm / vpdk55nm) so users can run the entire design flow out of the box without first acquiring a foundry NDA. They include full BSIM models + gm/Id lookup tables + corner files, exposing the complete design / simulation / optimization experience.

They are not substitutes for real processes — parameters do not correspond to any foundry, intended purely for teaching, algorithm validation, and product demos. For real tape-outs use sky130 (Apache-2.0 real open-source process) or install your own foundry PDK.

Bundled PDKs

Cirona ships 3 PDKs, located under the install dir's backend/pdk/:

PDK	Process	VDD	Use case	Tape-out
vpdk180nm	Generic 180nm BSIM3v3	1.8V core / 3.3V IO	Onboarding, teaching, algo validation	❌
vpdk55nm	Low-power 55nm BSIM4 v4.5	1.2V core / 1.8V IO	Low-noise / high-speed demos	❌
sky130	SkyWater open-source 130nm	1.8V	Real process	✅

Add your own PDK — one-click in Settings

Need a commercial foundry PDK (under NDA) or your own custom PDK? Add it through the Settings panel.

What the PDK Library section looks like:

┌─ PDK Library ───────────────────────────────────┐
│  ✓ vpdk180nm   bundled    🔒 (read-only)        │
│  ✓ vpdk55nm    bundled    🔒                    │
│  ✓ sky130      bundled    🔒                    │
│  ✓ tsmc28      D:\foundry\tsmc28\        🗑     │  ← yours, deletable
│                                                  │
│  [➕ Add PDK…]   [🔄 Refresh]                   │
└──────────────────────────────────────────────────┘

Five-step add operation:

1. Bottom-left ⚙️ Settings → scroll to PDK Library
2. Click ➕ Add PDK…
3. Pick the PDK directory in the system dialog (must contain config/pdk_config.json)
4. Name the PDK (letter-led, a-zA-Z0-9_-, 2–40 chars)
5. Cirona writes the absolute path you picked directly into the user-layer acp.yaml managed-block — no file copy, no junction. This is “reference mode”: WYSIWYG, the yaml entry equals what you picked

Once added, the PDK appears in the Settings list immediately (with source-path tooltip), and also in the New-Library dialog dropdown. No restart needed.

Optional modes (mode field on POST): junction additionally creates a junction at <APP_DATA_ROOT>/pdk/<name>/ (handy if you want all PDK references collected under one root for backup); copy deep-copies the source there (self-contained but takes disk space). Both are opt-in; the UI uses reference by default.

Delete: Settings → PDK Library → select → trash icon → confirm. Deletion only rmdirs the link itself — it never follows the junction to delete source files. Bundled PDKs are read-only.

Pick a PDK when creating a Library

Every new Library must choose a PDK:

1. Explorer → + New Project → choose Library type
2. Enter Library name + pick a PDK from the dropdown (3 bundled + ones you installed)
3. Cirona auto-creates a junction at <library>/pdk/<chosen-pdk>/ → real PDK location

Testbenches inside the library use relative paths like .lib “../../pdk/<pdk>/<lib>” tt; the first segment passes through the junction to land on the real PDK. This makes libraries backup / cross-machine portable as long as the junction is rebuilt.

Changing a Library's PDK after creation

To switch PDK for an existing library: right-click the Library name in Explorer → Change PDK… → pick the new PDK in the dropdown → Switch. Cirona replaces the <library>/pdk/ junction. Caveat: existing testbenches still reference the old PDK name in their .lib “../../pdk/<old-name>/...” strings (the directory name changes), so you'll need to update them by hand or regenerate the testbench.

Demo library is a special case

projects/demo/ is a mixed-PDK library (4 cells use vpdk180nm and vpdk55nm). Its pdk/ junction points at the PDK collection root, not a single PDK. The installer auto-creates this junction.

If the demo fails with “.lib not found”, the junction is broken (e.g. install moved, cross-machine copy without rebuild, manual delete). Fix: run scripts\install_demo_junction.bat (Windows) or scripts/install_demo_junction.sh (Unix) from the install directory — the script will rebuild the junction.

gm/Id characterisation data

Every bundled PDK ships with a gm_id_data/ subdir (gm/Id lookup tables) so the gmid_sizing skill can give immediate sizing advice without re-sweeping. Custom PDKs without these tables still work — sizing just falls back to live sweeps (slower).

Iron Laws

• Don't hand-edit acp.yaml or install.json to add PDKs — use Settings UI (which validates paths, names, and does junction-safe deletion).
• Don't copy PDK files into a library — libraries only hold junctions.
• Testbenches always use relative ../../pdk/<name>/<lib>, never absolute paths.

运行仿真

1. 打开 testbench 文件（如 tb_ac.sp）
2. 点击工具栏的 Run 按钮运行仿真
3. 在 Simulation 面板查看输出结果

支持的分析类型

分析	命令	用途
DC 工作点	.op	验证偏置点
DC 扫描	.dc	传输曲线、稳压特性
AC 分析	.ac	频率响应、稳定性
瞬态分析	.tran	时域行为

仿真引擎

使用 ngspice 作为仿真后端（Windows 上使用 ngspice_con.exe）。仿真路径在 .cirona/settings/.env 中配置 NGSPICE_PATH。

.measure 结果解析

仿真完成后，AI 自动解析 ngspice 输出中的 .measure 结果，提取增益、带宽、相位裕度等关键指标进行分析。

Running a Simulation

1. Open a testbench file (e.g., tb_ac.sp)
2. Click the Run button in the toolbar
3. View output results in the Simulation panel

Supported Analysis Types

Analysis	Command	Use Case
DC Operating Point	.op	Verify bias point
DC Sweep	.dc	Transfer curve, regulation characteristics
AC Analysis	.ac	Frequency response, stability
Transient Analysis	.tran	Time-domain behavior

Simulation Engine

Uses ngspice as the simulation backend (on Windows, uses ngspice_con.exe). Configure the path via NGSPICE_PATH in .cirona/settings/.env.

.measure Result Parsing

After simulation completes, the AI automatically parses .measure results from ngspice output, extracting key metrics like gain, bandwidth, and phase margin for analysis.

从 SPICE 网表自动生成可视化原理图，位于主面板的 Schematic 标签页。

精调布局（Curated Layout）

针对常见电路拓扑，提供经过精心排版的原理图布局：

电路类型	匹配关键词
五管 OTA	five_transistor_ota, 5t_ota, simple_ota
折叠共源共栅 OTA	folded_cascode_ota, fc_ota, fcota
套筒式 OTA	telescopic_ota, tele_ota
两级 OTA	two_stage_ota, miller_ota, miller_comp
StrongARM 比较器	strongarm, strong_arm
Bandgap 基准	bandgap_ref, bgr, bg_ref

拓扑识别 Fallback

对于非标准命名的电路，系统会：

1. 解析网表构建电路图（CircuitGraph IR）
2. 运行 6 个拓扑检测器（差分对、cascode 链、电流镜、PTAT 支路等）
3. 自动分配设备角色并进行智能布局

即使你的电路命名完全不标准（如 my_custom_amp），系统也能识别其拓扑结构并生成合理的原理图。

Automatically generates visual schematics from SPICE netlists, accessible via the Schematic tab in the main panel.

Curated Layouts

For common circuit topologies, carefully crafted schematic layouts are provided:

Circuit Type	Matching Keywords
Five-transistor OTA	five_transistor_ota, 5t_ota, simple_ota
Folded-cascode OTA	folded_cascode_ota, fc_ota, fcota
Telescopic OTA	telescopic_ota, tele_ota
Two-stage OTA	two_stage_ota, miller_ota, miller_comp
StrongARM Comparator	strongarm, strong_arm
Bandgap Reference	bandgap_ref, bgr, bg_ref

Topology-Recognition Fallback

For non-standard circuit names, the system:

1. Parses the netlist to build a circuit graph (CircuitGraph IR)
2. Runs 6 topology detectors (differential pair, cascode chain, current mirror, PTAT branch, etc.)
3. Automatically assigns device roles and performs intelligent layout

Even if your circuit has a completely non-standard name (e.g., my_custom_amp), the system can recognize its topology and generate a reasonable schematic.

基于 Plotly.js 的交互式波形可视化，位于主面板的 Waveform 标签页。

支持的波形类型

• Bode 图 — 双轴显示幅度（dB）和相位（度），自动标注增益、UGF、相位裕度
• 时域波形 — 瞬态仿真输出，支持多信号叠加
• DC 扫描曲线 — 传输特性、稳压曲线等

交互功能

• 鼠标拖拽缩放、双击复位
• 悬停查看精确数值
• 图例点击显示/隐藏信号

缩略图联动

AI 在对话中生成波形时会显示缩略图预览，点击缩略图可以在 Waveform 面板中查看完整的交互式波形。

Interactive waveform visualization powered by Plotly.js, accessible via the Waveform tab in the main panel.

Supported Waveform Types

• Bode Plot — Dual-axis display of magnitude (dB) and phase (degrees), with automatic annotation of gain, UGF, and phase margin
• Transient Waveforms — Time-domain simulation output with multi-signal overlay support
• DC Sweep Curves — Transfer characteristics, voltage regulation curves, etc.

Interactive Features

• Click-and-drag to zoom, double-click to reset
• Hover to view precise values
• Click legend items to show/hide signals

Thumbnail Linkage

When the AI generates a waveform during conversation, a thumbnail preview appears in the chat. Clicking the thumbnail opens the full interactive waveform in the Waveform panel.

会话持久化

每次对话自动保存，按项目路径绑定。切换项目时会自动保存当前会话并恢复目标项目的会话。

会话历史

历史会话存储在 <project>/.cirona/history/sessions/ 目录中。使用 /resume 命令可以列出并恢复历史会话。

Context 压缩（Compaction）

长对话会累积大量 token，Cirona 用两层压缩把 prompt 控制在窗口内，同时尽量不丢推理连续性：

• 微压缩（microcompact，自动） — 仿真类工具（simulate / dc_snapshot / op_point_check）每次输出都是 10–30 KB 的 ngspice 日志。这些工具只保留最近一次原文，更早的同类调用自动折叠成一行 verdict 摘要（“gain=70 dB / PM=68° / UGF=10 MHz”），AI 仍能看到趋势但不会被原始日志爆掉。
• 整窗压缩（/compact，手动 + 自动阈值） — context 接近模型上限时，会用 LLM 把早期对话压缩成一段“故事梗概”，保留电路标识符 + 关键数值 + 决策原因。手动可以输入 /compact 立即触发；自动会在阈值时先弹通知，你确认后才压。

压缩后 AI 仍能讨论早期内容，但精度退到摘要层（不会逐字回忆某轮 tool_use 参数）。需要精确细节请用 /resume 恢复历史会话或翻 events.jsonl。

Checkpoint 与回滚

AI 每次修改文件（write_file / edit_file）之前会自动创建一个 git checkpoint 记录当前 working tree 状态。设计走偏了用 /rewind 一键回到任一历史点：

/rewind              # 列出可用 checkpoint（带时间戳 + 简短描述）
/rewind <id>         # 回滚到指定 checkpoint

Metric Delta 表格

每个 checkpoint 自动附带 spec / sizing / pytest 指标（从 events.jsonl 解析最近一次 simulate / pvt_scan 输出）。/rewind <id> 完成后，前端会弹一张 前 / 后 / Δ 三列对比表，让你直观看到这次 rewind 拿掉了什么、加上了什么：

Metric              Before      After       Δ
─────────────────────────────────────────────────
spec.gain_db        72.3        68.1        -4.2
spec.pm_deg         62.0        72.5        +10.5
spec.ugf_mhz        15.2        12.8        -2.4
sizing.M1.W         24u         18u         -6u
sizing.Itail        100u        80u         -20u
pytest.passed       12          10          -2

支持的 spec 指标：gain (dB) / phase margin (°) / UGF (MHz) / bandwidth (MHz) / vout (V) / power (µW) / CMRR (dB)。sizing 字段从 spec.yaml / sizing.yaml 自动读出。指标采集失败不会阻止 checkpoint 创建（只是 delta 表格少几行）。

Memory 系统（跨 session 记忆）

Cirona 有一套结构化的跨 session 记忆系统，让 AI 在多轮对话和多个 session 之间记得你的偏好、项目决策、电路设计经验，不必每次重新解释。

三大类（user-facing category）

Category	存储位置	内容
user	全局 <APP_DATA_ROOT>/.cirona/memory/	关于“你”的偏好和反馈 — 例如“我习惯 NMOS 输入对”、“PSRR 我只关心 1 kHz–1 MHz 段”
project	项目级 <project>/.cirona/memory/	关于“这个项目”的决策和结果 — spec 解读、架构选择、关键测试结果、踩过的坑
circuit	全局（跨项目）	关于“这类电路”的可复用经验 — 例如“folded-cascode 的 PMOS cascode 用 4× 比例”，下次再设计同类电路自动用上

内部细分（fine-grained type）

每条 memory 还带一个细分 type，AI 自己决定用哪个：

• user 类：preference（偏好）/ feedback（用户纠正）
• project 类：project（项目元数据）/ decision（设计决策）/ result（关键结果）
• circuit 类：circuit（电路通用经验）/ lesson（失败教训）/ reference（参考实现）

怎么沉淀（agent 主动）

Memory 写入是 AI 的主动行为，不是手动指令。AI 觉得“这条值得跨 session 记住”时（你纠正了它一个误解、它发现了一个有效的 sizing 模式）会自动调 memory.save 工具沉淀下来。从 DevTools 的 Events 流里能看到它什么时候在写 memory。

怎么用（自动 inject）

每次新对话开始时，相关 memory（按 token budget 6000 + 向量相似度排序）会自动注入到 AI 的 system prompt。所以你不需要手动“召回”，AI 自己就带着上下文来了。

怎么读 / 改

所有 memory 是 Markdown + YAML frontmatter 的纯文本文件，可以直接打开看。在 Explorer 里展开 .cirona/memory/ 目录就能浏览，也能手动编辑（一般还是让 AI 自己管，但如果某条记错了可以手动改）。

设计经验（Lessons）

每次设计完成后，AI 可以将关键经验教训整理为 Lesson 文档，存储在 .cirona/lessons/ 目录中。

经验系统分为两层：

• Workspace 层（workspace/.cirona/lessons/）— 跨 Library 的通用经验
• Library 层（<library>/.cirona/lessons/）— 项目特定的设计经验

在左侧 Explorer 面板中，展开 Library 或 .ANALOG-COPILOT 区域可以看到 lessons 和 discussions 目录。点击 lessons 条目即可以 Markdown 预览模式查看内容。

设计讨论（Discussions）

跨 Library 的设计讨论存储在 workspace/.cirona/discussions/ 目录中，用于记录架构决策、方案对比等需要持久化的讨论内容。

Session Persistence

Conversations are saved automatically, bound to the project path. Switching projects saves the current session and restores the target project's session.

Session History

Historical sessions are stored in <project>/.cirona/history/sessions/. Use the /resume command to list and restore historical sessions.

Context Compression

Long conversations accumulate tokens fast. Cirona uses two layers of compression to keep the prompt within window while preserving reasoning continuity:

• Microcompact (automatic) — Simulation tools (simulate / dc_snapshot / op_point_check) emit 10–30 KB of ngspice log every call. These tools only keep the latest call verbatim; earlier calls of the same tool collapse into a one-line verdict (“gain=70 dB / PM=68° / UGF=10 MHz”) so the AI can still see the trend without the prompt exploding.
• Full-window compaction (/compact, manual + auto-threshold) — When context approaches the model's limit, an LLM call summarises early conversation into a “story digest” preserving circuit identifiers + key values + decision rationale. Type /compact to trigger immediately; the auto-threshold notifies you first and waits for confirmation.

After compaction the AI can still discuss earlier content, but precision drops to the digest level (it won't recall verbatim a specific tool_use's arguments). For exact details use /resume to restore a historical session, or browse events.jsonl.

Checkpoint & Rollback

The AI automatically creates a git checkpoint before every file modification (write_file / edit_file), capturing the current working tree. If the design goes wrong, /rewind restores any historical state with one command:

/rewind              # List available checkpoints (timestamp + short label)
/rewind <id>         # Roll back to a specific checkpoint

Metric Delta Table

Each checkpoint carries a spec / sizing / pytest snapshot (parsed from the latest simulate / pvt_scan result in events.jsonl). After /rewind <id>, the UI shows a Before / After / Δ table so you can see exactly what the rewind removed and added:

Metric              Before      After       Δ
─────────────────────────────────────────────────
spec.gain_db        72.3        68.1        -4.2
spec.pm_deg         62.0        72.5        +10.5
spec.ugf_mhz        15.2        12.8        -2.4
sizing.M1.W         24u         18u         -6u
sizing.Itail        100u        80u         -20u
pytest.passed       12          10          -2

Tracked spec metrics: gain (dB), phase margin (°), UGF (MHz), bandwidth (MHz), vout (V), power (µW), CMRR (dB). Sizing fields read from spec.yaml / sizing.yaml. Failed metric collection never blocks checkpoint creation — the delta just has fewer rows.

Memory System (Cross-Session Recall)

Cirona has a structured cross-session memory system so the AI remembers your preferences, project decisions, and circuit-design experience across multiple turns and multiple sessions, instead of re-explaining them every time.

Three categories (user-facing)

Category	Storage	Contents
user	Global <APP_DATA_ROOT>/.cirona/memory/	About you — preferences and corrections, e.g. “I default to NMOS input pairs”, “I only care about PSRR from 1 kHz–1 MHz”
project	Per-project <project>/.cirona/memory/	About this project — spec interpretation, architecture choices, key test results, gotchas hit
circuit	Global (cross-project)	About this kind of circuit — reusable patterns like “folded-cascode PMOS cascode at 4× ratio”, auto-applied next time you design a similar circuit

Fine-grained types

Each entry also has a fine-grained type — the AI picks one when saving:

• user: preference / feedback (your corrections)
• project: project (project metadata) / decision / result
• circuit: circuit (general lessons) / lesson (failure modes) / reference (working implementations)

How it gets written (agent-driven)

Memory writes are agent-initiated, not a manual command. When the AI judges that something is worth remembering across sessions (you corrected a misconception, it discovered an effective sizing pattern), it calls the memory.save tool itself. You can see these writes in the DevTools Events stream.

How it gets used (auto-injection)

At the start of each new conversation, relevant memory (sorted by vector similarity, capped at 6000 tokens) auto-injects into the AI's system prompt. You don't need to “recall” it — the AI walks in already aware.

How to read / edit

All memory is Markdown + YAML frontmatter plain text. Open the .cirona/memory/ directory in Explorer to browse. You can hand-edit too (usually best to let the AI manage it, but if it remembered something wrong you can fix it directly).

Design Lessons

After completing a design, the AI can organize key lessons into Lesson documents stored in .cirona/lessons/.

The lessons system has two layers:

• Workspace layer (workspace/.cirona/lessons/) — Cross-Library general experience
• Library layer (<library>/.cirona/lessons/) — Project-specific design experience

In the left Explorer panel, expand a Library or the .ANALOG-COPILOT area to see the lessons and discussions directories. Click a lessons entry to view it in Markdown preview mode.

Design Discussions

Cross-Library design discussions are stored in workspace/.cirona/discussions/, used to record architecture decisions, approach comparisons, and other content that needs to be persisted.

在对话输入框中输入 / 开头的命令执行特定操作。

内置命令

命令	功能
/help	显示命令快速参考面板
/clear	清空当前对话和会话
/compact	压缩上下文，释放 token 预算
/devtools	打开 DevTools 调试窗口
/model [name]	切换 LLM 模型
/plan	切换 Plan 模式（只分析不修改）
/rewind [id]	回滚文件到指定 checkpoint
/resume [id]	恢复历史会话
/skills [list|reload]	列出 / 重新扫描 Skill 目录（无参数默认 list）
/hooks	列出已注册的 Hook
/tools [list|reload]	列出 / 热重载自定义工具（无参数默认 list）
/export-pack <name>	将当前设计导出为 Pack 草稿

Skill 命令

已安装的 Skill 会自动注册为 slash 命令：

/skill list               # 列出已安装的 skill
/skill install <url>      # 安装新 skill
/skill remove <name>      # 卸载 skill

Type commands starting with / in the chat input box to perform specific operations.

Built-in Commands

Command	Function
/help	Show command quick reference panel
/clear	Clear the current conversation and session
/compact	Compress context to free up token budget
/devtools	Open DevTools debug window
/model [name]	Switch LLM model
/plan	Toggle Plan mode (analyze only, no modifications)
/rewind [id]	Roll back files to a specific checkpoint
/resume [id]	Restore a historical session
/skills [list|reload]	List / rescan the Skills directory (defaults to list)
/hooks	List registered Hooks
/tools [list|reload]	List / hot-reload custom tools (defaults to list)
/export-pack <name>	Export current design as a Pack draft

Skill Commands

Installed Skills are automatically registered as slash commands:

/skill list               # List installed skills
/skill install <url>      # Install a new skill
/skill remove <name>      # Uninstall a skill

电路 tutorial 章节正在整理中，将在后续版本提供。当前版本你可以通过 knowledge(action='catalog') 让 AI 列出所有内置电路 chapter，或直接打开 D:\CironaData\projects\demo\ 下的 4 个 demo cell（bandgap / fc_ota / two_stage / ldo）作为参考。

Circuit tutorial chapters are being curated and will ship in a future release. For now, ask the AI knowledge(action='catalog') to list all built-in circuit chapters, or open the 4 demo cells under D:\CironaData\projects\demo\ (bandgap / fc_ota / two_stage / ldo) as references.

文件操作

快捷键	功能
Ctrl+N	新建文件
Ctrl+O	打开文件夹
Ctrl+S	保存文件
Ctrl+Shift+S	保存所有文件
Ctrl+W	关闭当前 Tab

编辑器

快捷键	功能
Ctrl+Z	撤销
Ctrl+Y	重做
Ctrl+F	查找
Ctrl+H	替换
Ctrl+/	切换注释
Ctrl+D	复制当前行
Alt+Up/Down	移动行

视图

快捷键	功能
F1	打开帮助文档
Ctrl+K	快捷键列表
Ctrl+B	切换侧边栏
Ctrl+J	切换 AI 面板
F11	全屏

对话面板

快捷键	功能
Enter	发送消息
Shift+Enter	换行
ESC	取消当前 AI 操作

File Operations

Shortcut	Function
Ctrl+N	New file
Ctrl+O	Open folder
Ctrl+S	Save file
Ctrl+Shift+S	Save all files
Ctrl+W	Close current tab

Editor

Shortcut	Function
Ctrl+Z	Undo
Ctrl+Y	Redo
Ctrl+F	Find
Ctrl+H	Replace
Ctrl+/	Toggle comment
Ctrl+D	Duplicate current line
Alt+Up/Down	Move line up/down

View

Shortcut	Function
F1	Open help documentation
Ctrl+K	Shortcut reference
Ctrl+B	Toggle sidebar
Ctrl+J	Toggle AI panel
F11	Full screen

Chat Panel

Shortcut	Function
Enter	Send message
Shift+Enter	New line
ESC	Cancel current AI operation

后端无法启动

• 检查 Python 版本：python --version（需要 3.9+）
• 确认虚拟环境已激活
• 确认依赖已安装：pip install -r requirements.txt
• 检查 .cirona/settings/.env 文件是否存在且有有效的 API Key

前端无法启动

• 检查 Node.js 版本：node --version（需要 18+）
• 运行 pnpm install 安装依赖
• 清除缓存：pnpm store prune
• 确认后端已启动（前端不会自动启动后端）

仿真失败

• 确认 ngspice 已安装且路径配置正确（NGSPICE_PATH）
• Windows 用户确认使用的是 ngspice_con.exe，不是 ngspice.exe
• 检查网表语法（缺少 .ends、节点名错误等）
• 检查 PDK 路径是否正确
• 检查是否有悬空节点或短路

AI 没有响应

• 确认后端运行在正确端口（默认 8000）：访问 http://localhost:8000/health
• 检查 API Key 是否已配置（Settings 面板或 .env 文件）
• 确认 API 配额/余额充足
• 尝试用 /model 切换到其他模型
• 查看 DevTools 窗口（/devtools）的 Events 日志获取详细错误信息

原理图不显示

• 确认网表文件中有 .subckt 定义
• 确认已运行过至少一次仿真
• 尝试在编辑器中打开网表文件后切换到 Schematic 标签页

Backend Won't Start

• Check Python version: python --version (requires 3.9+)
• Confirm the virtual environment is activated
• Confirm dependencies are installed: pip install -r requirements.txt
• Check that .cirona/settings/.env exists and contains a valid API Key

Frontend Won't Start

• Check Node.js version: node --version (requires 18+)
• Run pnpm install to install dependencies
• Clear cache: pnpm store prune
• Confirm the backend is running (the frontend does not start the backend automatically)

Simulation Fails

• Confirm ngspice is installed and path is correctly configured (NGSPICE_PATH)
• Windows users: confirm you are using ngspice_con.exe, not ngspice.exe
• Check netlist syntax (missing .ends, wrong node names, etc.)
• Verify the PDK path is correct
• Check for floating nodes or short circuits

AI Not Responding

• Confirm the backend is running on the correct port (default 8000): visit http://localhost:8000/health
• Check that the API Key is configured (Settings panel or .env file)
• Confirm API quota/balance is sufficient
• Try switching to another model with /model
• Check the Events log in the DevTools window (/devtools) for detailed error information

Schematic Not Displaying

• Confirm the netlist file contains a .subckt definition
• Confirm at least one simulation has been run
• Try opening the netlist file in the editor, then switching to the Schematic tab

版本

Cirona 桌面版（Win-1.0）

技术栈

• 前端 — Electron + Monaco Editor + Plotly.js
• 后端 — Python + FastAPI + 自研 Agent Engine
• 仿真 — ngspice
• AI — Anthropic Claude / Gemini / DeepSeek / GLM / Kimi / MiniMax / OpenAI（多模型可选）
• 知识系统 — Pack 知识包 + Skill 方法库 + 14 base cell + 7 完整电路 chapter
• 可视化 — 原理图自动生成（7 curated + topology fallback）+ Plotly 波形 + LLM 智能布局

核心特色

• 知识驱动 — 不是通用 AI 套壳，而是融合了模拟电路设计知识的专业 Agent
• 开放生态 — Pack / Skill / Tool / Hook 四层可扩展
• 不依赖商业 EDA — 基于 ngspice + 开源 sky130 / 合成 vPDK 工具链
• 自研 Agent Engine — 多 LLM Provider 统一接入 + cache 命中率优化 + 跨 session 记忆

Version

Cirona Desktop (Win-1.0)

Technology Stack

• Frontend — Electron + Monaco Editor + Plotly.js
• Backend — Python + FastAPI + proprietary Agent Engine
• Simulation — ngspice
• AI — Anthropic Claude / Gemini / DeepSeek / GLM / Kimi / MiniMax / OpenAI (multi-model)
• Knowledge System — Pack knowledge modules + Skill method library + 14 base cells + 7 complete circuit chapters
• Visualization — Auto schematic generation (7 curated + topology fallback) + Plotly waveforms + LLM-driven layout

Key Differentiators

• Knowledge-driven — Not a generic AI wrapper; a specialized Agent deeply integrated with analog circuit design knowledge
• Open ecosystem — Four layers of extensibility: Pack / Skill / Tool / Hook
• No commercial EDA required — Built on open-source ngspice + open sky130 / synthetic vPDK toolchain
• Proprietary Agent Engine — Unified multi-LLM access + cache-hit optimization + cross-session memory