Cirona — An AI workbench for analog IC engineers

After the recent surge of AI coding tools, the industry has applied general-purpose agents to chip design and published widely on the topic. Research labs have built domain-specific agents for chip design too. Important work — meaningful exploration toward bringing AI into chip work. But what engineers really care about is: when can we actually use any of this conveniently?

We're shipping something different: an out-of-the-box, AI-native development platform for analog circuit design — Cirona.

What Cirona is · What it solves

Cirona addresses these engineer pain points

Today

Cirona

EDA toolchain install and configuration is painful

One-stop integrated environment, simple setup

Bridging AI and the EDA toolchain is hard

Drop in an API key, start working

Tuning LLMs for circuit-design domain is high-effort

Built-in analog-aware orchestration

Design experience binds to people, hard to transfer

Design experience packs up

Commercial PDKs are off-limits to individuals

Ships with vpdk (note)

Codex / Claude Code are essentially code-domain agents

An agent built for the analog IC design domain

Frontier LLMs unreachable in air-gapped networks

Cirona supports multiple LLMs (incl. CN models), can run offline

Note: vpdk = virtual PDK. Across foundries, the key device parameters of each generation (V_th / μC_ox / V_sat) tend to be similar — only the exact numbers differ. Real PDKs cannot be redistributed for legal reasons. We provide vpdk as a generic reference. A circuit designed on vpdk maps to a real foundry process with the same topology, sizing approach, and bias strategy — only fine parameter tweaks needed.

How to use

One OTA, from spec to schematic

Step 1

One-line spec

Open Cirona. Type one SPEC line in the right-hand chat panel.

DC gain ≥ 70 dB, GBW 50 MHz, phase margin > 60°, load cap = 1 pF, power < 500 µW; process vpdk180nm, Vdd = 1.8 V

Cirona · Welcome

Cirona · Project tree

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Step 2

AI derives topology and sizing

AI looks up the Pack knowledge base, traces from SPEC back to per-device W/L.

Cirona looks up the OTA design flow inside the Pack knowledge base. The AI picks a topology from the SPEC, back-solves g_m from GBW, back-solves current from power, allocates headroom by transistor role, and so on — getting W/L from the table.

Every formula and reasoning step is grounded. The user can interrupt and adjust at any point.

Cirona · Architecture select (1/2)

Cirona · Architecture select (2/2)

Cirona · Device sizing

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Step 3

Schematic output

The netlist is auto-written. Click the schematic toggle.

The netlist renders into a schematic automatically, so the engineer can review the actual circuit.

Cirona · FC-OTA schematic

Step 4

Simulation

Once the engineer signs off the schematic, Cirona writes the testbench and runs simulation.

When simulation finishes, every device's g_m, I_D, V_ds, V_ov appears in a table — saturation status visible at a glance. Bode plots, transient waveforms, node voltages all show up where you expect them.

Cirona · AC result

AC simulation: per-device DC operating point and small-signal metrics

Cirona · DC simulation

Cirona · Bode plot

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Step 5

Iterate / optimize

Sweeping 10 variables used to mean writing a wrapper and babysitting a batch run overnight.

Now one sentence:

Run an 80-trial optimization, maximize GBW, DC gain ≥ 70 dB, PM > 60°, 4-way concurrency.

Built-in Bayesian / CMA-ES / NSGA-II multi-objective optimizers. You see the achievable frontier of “gain vs power vs bandwidth” — not a single point.

Cirona · PVT corner sweep

Step 6

Capture the experience

Just finished a Two-Stage Miller with zero-nulling resistor? Click Pack Creator.

This run's netlist, bias strategy, and the traps you hit get bundled into a Pack. Next time the same topology comes up, install your Pack and the AI delivers the design seamlessly.

OPEN-SOURCE PACK REPO

github.com/nx-silicon/Cirona

First-batch Packs (OTA family / LDO / Bandgap / Comparator) shipping under GPL-3.0 — source fully open, derivative Packs stay open-source. Contributions welcome — bring your topology.

GPL-3.0 analog-IC Cirona Open repo →

Cirona executes ~80% of the work: sizing derivation, testbench writing, parameter optimization, data wrangling. But the key calls stay with the engineer: architecture direction, spec tradeoffs, what to verify. Every intermediate artifact surfaces in reviewable form: schematics, tables, Bode plots.

Cirona is the assistant that handles the tedious work. The engineer's thinking is still at the core.

Integrated demos

The current build ships with 4 demos

#

Circuit

Process

VDD

AI Provider

Result

01

PNP Brokaw Bandgap

vpdk180nm

1.8 V

Sonnet 4.6 / DeepSeek-v4-pro

✅ 5/5 PASScross-provider

02

Folded-Cascode OTA

vpdk180nm

1.8 V

Sonnet 4.6

✅ 5/5 PASS

03

2-stage Miller OTA

vpdk55nm

1.2 V

DeepSeek-v4-pro thinking

⚠️ 4/5 PASS + 1 marginal

04

PMOS-pass LDO

vpdk55nm IO Device

1.8 V → 1.2 V

Sonnet 4.6

✅ 11/11 PASS

Product feature

Packs — bottle the design experience

The greybeard analog wizard at your company — three decades of experience, head full of analog circuit know-how and traps, like: an architecture that breaks under a process change; LDO instability driven by output-current-dependent zero/pole shifts; a bandgap startup yield bug from a poorly designed startup circuit; the SDM-ADC capacitor-array mismatch fix.

None of it was ever written down. The day he retires, all of it walks out with him.

With Packs, an engineer's experience is preserved — permanently.

What is a Pack? Pack is short for knowledge package — a collection of circuit knowledge, design flow, and experience.

A Pack is organized as a directory. For example, the folded-cascode_ota Pack contains overview.md (what the topology is), design_flow.md (the design flow), reference_designs/ (reference netlists), failure_playbook.md (failure cases + diagnoses), lessons.yaml (historical lessons), skills/ (Pack-specific skills).

Cirona · Pack overview

Pack overview: directory structure and dependencies

A Pack is not a Skill

Skills are a hot concept in the AI space right now. A Skill is a prompt template describing how to do a class of work — generic, decoupled from industry and process. That paradigm fits general-purpose agents. It doesn't survive contact with analog IC.

Skill generic methodology template

Pack analog IC domain knowledge package

What it solves

Describes how to do a class of work

Loads the full design experience for one specific topology

Bound to

Not industry, process, or topology

Process, topology, corner behavior

Contents

System prompt fragments

Design flow + reference netlists + failure cases

Distribution

Inlined into the prompt

Like an npm package: declared deps, versioned, independently published

Who can contribute

Anyone who's written a generic prompt template

An analog engineer who has actually swept corners and hit traps on this topology

Cirona also supports analog-design Skill integration

The current build includes Analog Design Flow, Device Sizing, Netlist Review, SDAS (Spec-Driven Architecture Screening), and more — accessible from the Skill panel on the left of the UI. You can drop in your own Skills too.

Cirona · Skill panel

Cirona · Device Sizing

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How Packs are built

The simplest path: after finishing a design, type into the chat window — “Please bundle this design method and flow into a Pack.” Cirona walks you through the rest, dropping the Pack into your local working directory.

Open-source Pack community

One engineer ships a Pack for a new topology — every agent with that Pack installed gains a new capability. A thousand engineers each contributing one Pack — the agent gains a thousand capabilities.

This is what we care about most. The Pack repo is hosted on GitHub under GPL-3.0 — source fully open, derivative Packs stay open-source so the community keeps compounding. We hope it becomes an open-source community where everyone contributes Packs and AI's analog circuit design ability keeps growing.

We've already written the first batch of Packs (OTA family / LDO / Bandgap / Comparator). The next round of Pack library expansion is in progress — covering ADC / PLL / more OTA variants (class-AB, three-stage opamp, etc.). Contributions are welcome.

github.com/nx-silicon/Cirona · GPL-3.0

Product roadmap

Cirona product roadmap

Now · Win-1.0

Cirona Desktop (Windows)
- 4 base analog circuit demos: OTA family (FC-OTA / Two-Stage) / LDO / Bandgap
- 6-LLM-provider switching (Anthropic / DeepSeek / Gemini / GLM / Kimi / MiniMax)
- Schematic display, simulation waveform display
- Pack / Skill / Hook multi-source loading, contributable and distributable
- Modern optimizers (Bayesian / CMA-ES / NSGA-II multi-objective Pareto frontier) + PVT corner sweep
Current
On the way · Linux-1.0

Cirona Desktop (Linux)

Linux environment + HSpice / Spectre simulators + Virtuoso integration.
In progress
On the way · Enterprise

Cirona Enterprise

On-prem LLM deployment, customized to enterprise requirements.
Planned

How to download

Get Cirona

Runs locally. Bundled SPICE simulator, mainstream open-source PDKs included.

Windows desktop Current

v1.0.0-rc9.18 · 2026

Windows 10 / 11, x64
≥ 8 GB RAM recommended
Bundled NgSpice / ACS simulator
Includes vpdk180nm / vpdk55nm reference processes

Download installer (≈ 169 MB)

Linux desktop In progress

Linux-1.0

Ubuntu 22.04+ / Fedora 40+
HSpice / Spectre integration
Virtuoso bridge

GitHub Pack repo GPL-3.0

(TBD)

OTA family / LDO / Bandgap / Comparator at launch
Source fully open — read, modify, derive freely
Contributions welcome

Browse the Pack repo

Websitehttp://nx-si.ai/

Contactcontact@nx-si.com

IssuesGitHub Issues

User guidehelp.html

About

NX-Si AI

Take AI in the analog IC vertical from “looks like it works” to “does it right, repeatedly.”